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value
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Advantage
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Programmable system integration
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Up to 5.5M system logic unit, using 20nm process, and 2nd generation 3D IC
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Integrated 100G Ethernet MAC and 150G Interlaken core
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Improved system performance
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High utilization rate increases the speed by two levels
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30G Transceiver: 28G backplane for chip-to-chip and chip-to-fiber
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16G backplane transceiver with half power consumption
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2400Mb/s DDR4 can work stably under different PVT conditions
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BOM cost reduction
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Cost reduction by up to 50% – ½ of the cost per port of the Nx100G system
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The integration of VCXO and fPLL (frequency-divided phase-locked loop) can reduce the cost of clock components
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Mid-range speed grade chip can support 2400 Mb/s DDR4
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Total power consumption reduction
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Up to 40% lower power consumption compared to the previous generation
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Realize fine-grained clock gating function through an ASIC-like clock
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Enhanced system logic unit packaging reduces dynamic power consumption
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Accelerate design productivity
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Pin compatible with Kintex® UltraScale devices, high scalability
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Seamless pin migration from 20nm plane to 16nm FinFET
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Co-optimize with Vivado® Design Suite to accelerate design closure
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